This invention relates to superconducting circuits and, more particularly, to synchronous, digital superconducting logic circuits.
Josephson junctions have the ability to switch from the zero voltage state to a non-zero voltage state in times on the order of picoseconds, with the switching being limited by the resistive-capacitive time constant of the junction. Both hysteretic and non-hysteretic Josephson junctions have been used to construct high speed circuits having low power dissipation. There are two physical principles upon which data can be stored in Josephson logic systems. The first approach is to encode the stored data as a voltage across the Josephson junction. The second approach is to encode the stored data as magnetic flux trapped in a persistent superconducting loop. The smallest amount of magnetic flux for which the latter approach can be applied is a single flux quantum .phi..sub.0.
There are two physical principles upon which data can be transferred throughout a Josephson logic system. The first approach is to encode the data to be transferred as an electric current. The second approach is to encode the data to be transferred as a voltage pulse, V. For single flux quanta, the area of the voltage pulses over a period of time that will allow logic functions to be performed within the superconducting loops is equal to .phi..sub.0.
The logic representation used in superconducting circuits is vitally important to how the circuits perform signal inversion. In classical representation, where a logic TRUE is represented by a positive voltage and a logic FALSE is represented by a zero voltage, signal inversion must be accomplished by timed inversion. Since the superconducting phenomena does not support a three terminal transistor-like circuit, all state-of-the-art superconducting digital electronic circuits have only achieved signal inversion by signal interaction with an auxiliary timing signal. This timed inversion feature inherent in state-of-the-art superconducting digital electronic circuits limits their processing speed.
One type of superconducting digital logic circuit encodes a binary unity/zero as the presence/absence of a DC voltage across an unshunted Josephson tunnel junction. With a hysteretic current/voltage curve such "latching" circuits must be AC powered so that they can be reset to the initial superconducting state and this resetting must be slow enough to avoid punch through effects.
A second type of superconducting digital logic circuit uses the presence/absence of a single flux quanta in superconducting quantum interferometers to store the information. Such circuits are termed Resistive or Rapid Single Flux Quantum (RSFQ) circuits. General background information on RSFQ circuits can be found in an article by A. O. Mukhanov et al. entitled, "Ultimate Performance of the RSFQ Logic Circuits.", in IEEE Transactions on Magnetics, Vol. MAG-23, No. 2, March 1987, and an article by K. K. Likharev and V. K. Semenov, entitled "RSFQ Logic/Memory Family: A New Josephson-Junction Technology for SubTeraHertz-Clock-Frequency Digital Systems", in IEEE Transactions on Applied Superconductivity, Vol. 1, No. 1, March 1991.
RSFQ logic circuits are timed or clocked circuits, that is, they need two signals to define the information, a timing signal to define the interval for valid data and a data signal for defining the data being transmitted. This approach slows the speed at which data can be transmitted by a factor of 2. In addition, RSFQ circuits are asynchronous so they must trap and store intermediate calculations for future readout. This feature forces the inclusion of interferometers in each logic circuit. Interferometers, even for single magnetic flux quanta trapping, are spatially large circuits.
It is therefore desirable to devise a family of superconducting digital logic circuits which do not require an AC bias source, a separate timing signal, or the use of interferometers in each logic circuit. A commonly assigned application entitled, "Superconducting Push-Pull Flux Quantum Logic Circuits", filed concurrently herewith (U.S. Ser. No. 744,729), discloses such a family of superconducting digital logic circuits. The present invention seeks to utilize circuits from that family, and variations thereof, to construct gate array cells and to use such cells to perform logical operations on the data.